The present invention concerns a CMOS input buffer which stably operates for the variation of a power supply voltage.
When a CMOS integrated circuit is designed to receive TTL (transistor-transistor logic) level signals, its inputting stage is conventionally used as an input buffer which can convert the TTL level signals to the CMOS level signals. Typically, the CMOS input buffer converts the TTL level input signals such as address or data, to the CMOS level signals. The logic HIGH signal of the TTL level is defined between 2.2 volts and 5 volts, and the logic LOW signal thereof between 0 volt and 0.8 volt. Hence, the CMOS input buffer is in the worst case required to convert the TTL levels of 0.8 volt and 2.2 volt respectively to the logic LOW (ground voltage) and the logic HIGH (the power supply voltage Vcc). Conventionally, as the input buffer mainly is a NOR gate, it used NOR gate. It is preferable to maintain the trip point voltage of the NOR gate near the TTL mid-range voltage of 1.5 volt. However, the NOR gate has an inherent defect that the trip point voltage fluctuates according to variation of the power supply voltage Vcc. Consequently, the CMOS semiconductor memory allowing the variation of the power supply voltage to the range of 5 V.+-.10% requires a CMOS input buffer capable of operating stably and surely within such a range of the variation.